IMPLEMENTATION OF AN EFFICIENT PSEUDORANDOM BIT GENERATION METHOD AND ITS VLSI ARCHITECTURE

Abstract

Hence, data security has become a top priority. Cryptographic methods help resource-constrained smart devices encrypt and decrypt data. This protects data. PRBGs generate pseudo-random binary sequences from seeds. The cryptographic method's essential building element assures data secrecy. Academic research has used PRBG methods to generate pseudorandom bit sequences. Blum-Blum-Shub (BBS) PRBG is unexpected and cryptographically safe. BBS implementation requires huge integer modular multiplication. This makes the process computationally slow or costly. Han-Carlson adders and Montgomery modular multiplication are proposed for a low-latency BBS design. This will significantly reduce crucial route and computational delay. While improving the critical path, this technique has O(2n) clock delay due to recurrent calculation. This constraint necessitates research on a low hardware complexity coupled-LCG (CLCG) approach. CLCG uses a smaller region, reduced latency, and longer durations than BBS. Nevertheless, it fails the spectrum test, which can be rectified by dual-coupling four LCGs. The dual-CLCG approach requires inequality equations to obtain a valid one-bit random outcome. Inequality equations govern this procedure. Inequality equations slow the hardware implementation of the dual-CLCG approach for pseudorandom bit generation at every uniform clock rate. The thesis proposes a memory-based dual-CLCG architecture to solve this challenge. This architecture creates pseudorandom bits periodically. Its drawbacks include a high beginning clock delay, needless memory use, and a shorter sequence duration than other algorithms. This thesis presents two new PRBG algorithms and VLSI designs to solve these problems. These approaches create a pseudorandom bit every clock cycle with simple electronics. Both methods achieve the maximum length sequence and consistently pass all fifteen NIST benchmark tests. The recommended designs are built using Verilog HDL and prototyped using a commercial FPGA device in a lab. PRBG algorithms may assist produce pseudorandom bits in hardware security applications.